The present invention relates to an address signal storage circuit of a data repair controller. More particularly, the present invention relates to such an address signal storage circuit of a data repair controller which is disabled by an external control signal to reduce current dissipated during enabling when the data repair operation of a redundancy circuit is controlled to be disabled, and stably stores an address signal of a prescribed level according to the connection and disconnection of a fuse when the data repair operation of the redundancy circuit is controlled to be enabled.
Referring to FIG. 1, there is shown a prior art address signal storage circuit of a data repair controller. A level stabilizer 1 stabilizes an output signal level to a constant level by a level control signal LC applied from the exterior when a fuse is shorted. A control signal generator 2 generates control signals SWS1 and SWS2 for storing an address signal AD of a prescribed level by the output signal of the level stabilizer 1 according to the connection and disconnection of the fuse. A signal storage portion 3 stores the address signal AD of the prescribed level by the control signals SWS1 and SWS2 generated from the control signal generator 2.
The level stabilizer 1 includes PMOS transistors PM1 and PM2 having respective source electrodes commonly connected to a power voltage VCC terminal, respective gate electrodes respectively connected to the level control signal LC and the control signal SWS1 of the control signal generator 2 and respective drain electrodes commonly connected to one terminal of the fuse, and a PMOS condenser MC having drain and source electrodes commonly connected to the power voltage VCC terminal.
The control signal generator 2 includes an inverter I1 for generating the control signal SWS1 by inverting the output signal of the level stabilizer 1 according to the connection and disconnection of the fuse, and an inverter I2 for generating the control signal SWS2 by inverting the control signal SWS1 generated from the inverter I1.
The signal storage portion 3 has a transmission gate TG1 switched by the control signals SWS1 and SWS2 generated from the inverters I1 and I2 of the control signal generator 2 to generate the address signal AD of the prescribed level, and a transmission gate TG2 switched by the control signals SWS1 and SWS2 to generate an inverted address signal which has passed through an inverter I3.
Referring to FIG. 2, another prior art address storage circuit of the data repair controller is shown. Level stabilizers 10 and 20 stabilize an input signal level to a constant level when fuses FUSE1 and FUSE2 are in the connected state. A signal storage portion 30 generates a signal of a constant level irrespective of address input signals Ai and /Ai after disabled by signals stabilized by the level stabilizers 10 and 20 when the fuses FUSE1 and FUSE2 are in the connected state, and generates an inversion signal of the signal generated when disabled by storing the input address signal Ai of a prescribed level after enabled by an input signal when the connected state of the fuses FUSE1 and FUSE2 is different.
The level stabilizer 10 includes an NMOS transistor NM1 having a drain electrode connected to one terminal of the fuse FUSE1 and an input terminal of an inverter I10, a gate electrode connected to an output terminal of the inverter I10, and a source electrode connected to a ground voltage VSS terminal.
The level stabilizer 20 includes an NMOS transistor NM6 having a drain electrode connected to one terminal of the fuse FUSE2 and an input terminal of an inverter I11, a gate electrode connected to an output terminal of the inverter I11, and a source electrode connected to the ground voltage VSS terminal.
In the signal storage portion 30, a PMOS transistor PM1 has a source electrode commonly connected to the power voltage VCC terminal and the other terminals of the fuses FUSE1 and FUSE2, and a gate electrode connected to the drain electrode of the NMOS transistor NM1 of the level stabilizer 10. A PMOS transistor PM2 has a source electrode connected to a drain electrode of the PMOS transistor PM1, and a gate electrode connected to the address signal Ai. An NMOS transistor NM2 has a drain electrode commonly connected to a drain electrode of the PMOS transistor PM2 and an output signal OS, and a gate electrode connected to the inverted address signal /Ai. An NMOS transistor NM3 has a drain electrode connected to a source electrode of the NMOS transistor NM2, a gate electrode connected to the gate electrode of the PMOS transistor PM1, and a source electrode connected to the ground voltage VSS terminal. A PMOS transistor PM3 has a source electrode connected to the source electrode of the PMOS transistor PM1, and a gate electrode connected to the drain electrode of the NMOS transistor NM6 of the level stabilizer 20. A PMOS transistor PM4 has a source electrode connected to a drain electrode of the PMOS transistor PM3, and a gate electrode connected to the inverted address signal /Ai. An NMOS transistor NM4 has a drain electrode commonly connected to a drain electrode of the PMOS transistor PM4 and the output signal OS, and a gate electrode connected to the address signal Ai. An NMOS transistor NM5 has a drain electrode connected to a source electrode of the NMOS transistor NM4, a gate electrode connected to the gate electrode of the PMOS transistor PM3, and a source electrode connected to the ground voltage VSS terminal.
The operation of the address signal storage circuits of the data repair controller constructed in the above-mentioned way will now be described.
Referring again to FIG. 1, it is assumed that an output signal FOUT of the signal storage portion 3 should be set to logic "high" in order to control the data repair operation of a redundancy circuit (not shown) to be disabled. The fuse is externally controlled to a connected state.
Since the fuse is in the connected state, the ground voltage VSS is applied to the node N1 and the node N1 is set to logic "low". The inverter I1 of the control signal generator 2 generates the control signal SWS1 of logic "high", and the inverter I2 generates the control signal SWS2 of logic "low". The transmission gate TG1 of the signal storage portion 3 receives the control signal SWS2 of logic "low" generated from the inverter I2 and the control signal SWS1 of the logic "high" generated from the inverter I1 through PMOS and NMOS terminals, respectively. Therefore, the transmission gate TG1 is turned on and generates the input address signal AD of logic "high". Thus, the redundancy circuit is disabled by the address signal AD of logic "high" generated from the transmission gate TG1 of the signal storage portion 3. Consequently, in order to control the data repair operation of the redundancy circuit to be disabled, the signal storage portion 3 stores the address signal AD of logic "high".
On the other hand, in order to control the data repair operation of the redundancy circuit to be enabled, it is assumed that the output signal FOUT of the signal storage portion 3 should be set to logic "low". If the fuse is in the connected state, the transmission gate TG1 of the signal storage portion 3 is turned on by the control signals SWS1 and SWS2 generated from the control signal generator 2, as described above, and generates the input address signal AD of logic "low".
If the fuse is shorted, the node N1 is set to logic "high" by the PMOS transistors PM1 and PM2 and the PMOS condenser MC. The inverter I1 generates the control signal SWS1 of logic "low", and the inverter I2 generates the control signal SWS2 of logic "high". The transmission gate TG2 of the signal storage portion 3 receives through a PMOS terminal the control signal SWS1 of logic "low" generated from the inverter I1 and through an NMOS terminal the control signal SWS2 of logic "high" generated from the inverter I2. Therefore, the transmission gate TG2 is turned on and generates the output signal FOUT of logic "low" which inverts the address signal AD of logic "high" by the inverter I3.
Consequently, in order to control the data repair operation of the redundancy circuit to be disabled, the signal storage portion 3 stores the input address signal AD of logic "high" while the fuse is connected. In order to control the data repair operation of the redundancy circuit to be enabled, the signal storage portion 3 stores the input address signal AD of logic "low" while the fuse is connected, and stores the input address signal AD of logic "high" while the fuse is shorted.
Referring now to FIG. 2, in order to control the data repair operation of the redundancy circuit to be disabled, the fusses FUSE1 and FUSE2 are controlled to the connected state. Since the fuse FUSE1 is in the connected state, a node N1 is set to logic "high", and the logic "high" voltage across the node N1 is applied to the gate electrode of the NMOS transistor NM1 through the inverter I10. Therefore, the NMOS transistor NM1 is turned off and that node N1 is in the stabilized logic "high" voltage. Moreover, a node N2 is set to logic "high" since the fuse FUSE2 is in the connected state, and the logic "high" voltage across the node N2 is applied to the gate of the NMOS transistor NM6 through the inverter I11. Hence, the NMOS transistor NM6 is turned off and the that node N2 is in the stabilized logic "high" voltage.
The logic "high" voltages across the nodes N1 and N2 are applied to the gate electrodes of the NMOS transistors NM3 and NM5, respectively. The NMOS transistors NM3 and NM5 are turned on and the output signal OS is set to logic "low" irrespective of the input address signals Ai and /Ai. Thus, the redundancy circuit is disabled by the output signal of logic "low" generated from the signal storage portion 30.
In order to control the repair operation of the redundancy circuit to be enabled, if the fuse FUSE1 is shorted and the fuse FUSE2 is connected, the node N1 is set to logic "low" and the node N2 is set to logic "high". Then the signal storage portion 30 receives the logic "low" voltage across the node N1 and the logic "high" voltage across the node N2 and stores the input address signal Ai of logic "low", thereby generating the output signal OS of logic "high".
That is, the PMOS transistor PM1 and the NMOS transistor NM3 of the signal storage portion 30 receive the logic "low" voltage across the node N1 through the respective gate electrodes, and are turned on and turned off, respectively. The PMOS transistor PM2 and the NMOS transistor NM4 receive the address signal Ai of logic "low" through the respective gate electrodes, and are turned on and turned off, respectively. The NMOS transistor NM2 and the PMOS transistor PM4 receive the inverted address signal /Ai of logic "high" through the respective gate electrodes, and are turned on and turned off, respectively. The PMOS transistor PM3 and the NMOS transistor NM5 receive the logic "high" voltage across the node N2 through the respective gate electrodes, and are turned off and on, respectively. Therefore, the signal storage portion 30 generates the output signal OS of logic "high". The redundancy circuit is enabled by the output signal OS of logic "high" and carries out the data repair operation.
In order to control the repair operation of the redundancy circuit to be enabled, if the fuse FUSE1 is in the connected state and the fuse FUSE2 is in the shorted state, the node N1 is set to logic "high" and the node N2 is set to logic "low". Then the signal storage portion 30 receiving the logic "high" voltage across the node N1 and the logic "low" voltage across the node N2 stores the address signal Ai of logic "high" and generates the output signal OS of logic "high".
In more detail, the PMOS transistor PM1 and the NMOS transistor NM3 receiving the logic "high" voltage across the node N1 through the respective gate electrodes are turned off and turned on, respectively. The PMOS transistor PM2 and the NMOS transistor NM4 receiving the address signal Ai of logic "high" through the respective gate electrodes are turned off and turned on, respectively. The NMOS transistor NM2 and the PMOS transistor PM4 receiving the inverted address signal/Ai of logic "low" through the respective gate electrodes are turned off and turned on, respectively. The PMOS transistor PM3 and the NMOS transistor NM5 receiving the logic "low" voltage across the node N2 through the respective gate electrodes are turned on and turned off, respectively. Therefore, the output signal OS of logic "high" is generated.
As a result, in order to enable the data repair operation of the redundancy circuit, if the fuse FUSE1 is in the shorted state and the fuse FUSE2 is in the connected state, the address signal Ai of logic "low" is stored. If the fuse FUSE1 is in the connected state and the fuse FUSE2 is in the shorted state, the address signal Ai of logic "high" is stored.
However, since the prior art address storage circuit of the data repair controller should store the address signal of the prescribed level in order to control the data repair operation to be disabled, as shown in FIG. 1, the current is dissipated by such operation and the power consumption increases. Further, as shown in FIG. 2, since the address signal is stored using two fuses, the area occupied by the address storage circuit increases. If both fusses are shorted, since the logic "low" level across the shorted nodes is not stabilized, the address storage circuit operates unstably and another level stabilizer is needed.